{"id":16939,"date":"2026-10-01T15:17:35","date_gmt":"2026-10-01T08:17:35","guid":{"rendered":"https:\/\/pmac.asia\/chip-bao-mat-vgc-v1-0-viet-nam\/"},"modified":"2026-11-09T15:46:37","modified_gmt":"2026-11-09T08:46:37","slug":"vietnam-vgc-v1-0-security-chip","status":"publish","type":"post","link":"https:\/\/pmac.asia\/en\/vietnam-vgc-v1-0-security-chip\/","title":{"rendered":"Vietnam Unveils the VGC v1.0 Security Chip: From a Domestic Cipher to Working Silicon"},"content":{"rendered":"

One of the first applications shown at the VGC v1.0 launch in Hanoi on November 3, 2026, was a secure USB storage device. Inside it, a dedicated circuit performs cryptographic operations using a cipher developed in Vietnam. The device is a tangible outcome of the partnership between the Vietnam Government Information Security Commission<\/a> and Viettel: the team translated a cryptographic specification into a chip design, tested the first silicon and integrated it into a working product.<\/p>\n

The announcement also raises a question that matters to semiconductor manufacturers and technology buyers: which parts of the development process did the Vietnamese team carry out? Chip architecture, wafer fabrication and device qualification are distinct activities. Understanding the contribution of VGC v1.0 requires looking at the evidence for each.<\/p>\n

I. What Does VGC v1.0 Do Inside a Device?<\/strong><\/h2>\n

VGC v1.0 is a purpose-built security chip. One of its central functions is to execute MKV<\/strong>, a Vietnamese block cipher specified in national standard TCVN 14263:2024. A block cipher processes fixed-size blocks of data using a cryptographic key. The algorithm defines the required transformations, while the chip designer determines how a circuit will perform them.<\/p>\n

Secure USB storage illustrates the distinction. When a file needs to be encrypted, the device must carry out the transformations defined by the cipher. VGC v1.0 assigns that work to a dedicated hardware block, allowing engineers to test the implementation and measure its performance on physical silicon.<\/p>\n

\"L\u00e3nh

Figure 1. Delegates visit the technology exhibition area at the groundbreaking ceremony for Viettel\u2019s semiconductor chip manufacturing plant in Hoa Lac on January 16, 2026.<\/p><\/div>\n

II. <\/strong>What Changes When a Cipher Is Implemented in Hardware?<\/strong><\/h2>\n

1. <\/strong>Translating a cryptographic specification into a circuit<\/strong><\/h3>\n

A software implementation uses a processor to execute instructions for each cryptographic operation. A hardware implementation gives the designer control over how data moves through the circuit. The engineering task is to make those circuits produce the result required by the cipher across the intended operating conditions.<\/p>\n

For VGC v1.0, the Commission\u2019s M2 unit defined security requirements, developed the cryptographic solution and established evaluation criteria. Viettel\u2019s semiconductor team designed the integrated circuit and brought its functional blocks together on the chip. This division of responsibilities connected the team that understood the cipher with the engineers responsible for making it work in silicon.<\/p>\n

2. <\/strong>Interpreting the reported performance gain<\/strong><\/h3>\n

The developers reported that VGC v1.0 performed encryption and decryption approximately 15 times as fast<\/strong> as a software-only implementation in the same task. The comparison gives engineers a measure of the benefit achieved by moving that workload into dedicated hardware.<\/p>\n

A USB user experiences the time taken to complete an entire file transfer. That includes moving the data across the interface and writing it to memory. If storage write speed is the limiting factor, accelerating encryption will deliver a smaller gain in overall transfer speed. An end-to-end device test is therefore the appropriate measure for this use case.<\/p>\n

\"C\u1eadn

Figure 2. A close-up view of the VGC v1.0 chip on the circuit board, showcasing a secure hardware product developed by a Vietnamese team.<\/p><\/div>\n

III. Which Stages of Chip Development Did Vietnam Carry Out?<\/strong><\/h2>\n

Three specifications are frequently cited together for VGC v1.0: RISC-V<\/strong>, 28 nm CMOS<\/strong> and 10 \u00d7 10 mm<\/strong>. Each belongs to a different engineering decision. RISC-V concerns the processor design, the process node concerns fabrication, and the package dimensions matter when integrating the component onto a board.<\/p>\n\n\n\n\n\n\n\n\n
Stage<\/strong><\/td>\nPublished information<\/strong><\/td>\nTechnical significance<\/strong><\/td>\n<\/tr>\n
Processor design<\/td>\nThe processor uses the open RISC-V instruction set architecture.<\/td>\nThe instruction set defines the operations supported by the processor. The design team implements and verifies the circuitry that executes them.<\/td>\n<\/tr>\n
Cryptographic integration<\/td>\nA dedicated block implements the MKV cipher.<\/td>\nThe Vietnamese cryptographic design runs directly in hardware.<\/td>\n<\/tr>\n
Wafer fabrication<\/td>\nThe chip uses a 28 nm CMOS process.<\/td>\nThe node identifies the fabrication technology. The disclosed specifications do not identify the wafer fabrication site for the initial lot.<\/td>\n<\/tr>\n
Packaging<\/td>\nThe packaged device measures 10 \u00d7 10 mm.<\/td>\nThese are the external component dimensions used in board layout.<\/td>\n<\/tr>\n
Testing<\/td>\nThe first lot completed technical testing in the first quarter of 2026 and received certification for use in the economic and social sectors.<\/td>\nThe result applies to the scope of use covered by the assessment.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Specifications and certification scope are drawn from the Commission\u2019s launch announcement and technical account.<\/em><\/p>\n

The handoff to the fabrication facility is particularly important for a security chip. The developers describe measures taken to protect design data before it was transferred to the manufacturer. The published record establishes Vietnam\u2019s role in designing the chip and its cryptographic functions. It leaves the location of wafer fabrication for the first lot unspecified.<\/p>\n

IV. Secure USB Storage and Digital Signature Tokens<\/strong><\/h2>\n

Secure USB storage is an early application reported for VGC v1.0. The Commission has also identified USB tokens for digital signatures as a prospective application. The products may look similar, but they protect different assets and require different tests.<\/p>\n\n\n\n\n\n\n
Consideration<\/strong><\/td>\nSecure USB storage<\/strong><\/td>\nUSB signature token<\/strong><\/td>\n<\/tr>\n
Primary task<\/td>\nStore and retrieve protected files.<\/td>\nAuthorize and generate a digital signature.<\/td>\n<\/tr>\n
Asset to protect<\/td>\nData held on the device.<\/td>\nThe private signing key and its authorized use.<\/td>\n<\/tr>\n
Reported status for VGC v1.0<\/td>\nEarly application demonstrated.<\/td>\nIdentified as a future integration direction.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

A storage-device evaluation might focus on how protected files are written, retrieved and decrypted. A signature-token evaluation must also address how the device manages its private key and under what conditions it permits a signing operation. Success in one application informs the next design, but each device still requires testing against its own requirements.<\/p>\n

\"H\u00ecnh

Figure 3. A digital signature is an application of cryptographic technology that supports the authentication and protection of the integrity of electronic documents.<\/p><\/div>\n

V. <\/strong>From a Single Chip to Reusable Cryptographic IP<\/strong><\/h2>\n

One proposed next step is to turn the cryptographic design into a reusable hardware IP core<\/strong>. The deliverable would be a circuit design supported by interface documentation, operating requirements and tests. A new chip team could then integrate the function into its own architecture.<\/p>\n

Consider a storage controller and a device that protects data in transit. Both may need encryption, yet they handle different traffic patterns and throughput requirements. A reusable core becomes valuable when the receiving team can connect it to the surrounding system, understand its constraints and verify the result. This is how the engineering work behind VGC v1.0 could extend beyond the first product.<\/p>\n

VI. <\/strong>PMAC\u2019s Perspective: From Circuit Design to Wafer Quality<\/strong><\/h2>\n

During design verification, engineers ask whether the cryptographic circuit performs the specified operation. During fabrication<\/a>, the question changes: have the intended structures and material layers been formed correctly on the wafer? The distinction matters because a correct design and a well-controlled manufacturing process require different tools and evidence.<\/p>\n

Wafer surface preparation<\/a> offers a practical example. Before the next layer is formed, a manufacturer needs to identify the contamination to remove, the exposed materials to preserve and the measurement that will confirm the result. These are the conditions PMAC considers when helping manufacturers evaluate cleaning equipment, process chemicals and metrology options.<\/p>\n

VII. <\/strong>Frequently Asked Questions About VGC v1.0<\/strong><\/h2>\n

1. Why did the public launch follow testing by several months?<\/strong><\/h3>\n

The dates refer to different milestones. The first chip lot completed technical testing in the first quarter of 2026. The Commission and Viettel publicly introduced the chip and its secure semiconductor platform on November 3, 2026<\/strong>.<\/p>\n

2. <\/strong>Does the 28 nm process determine the chip\u2019s security level?<\/strong><\/h3>\n

The node identifies the technology used to fabricate the integrated circuit. Evaluating security requires separate evidence about the algorithm, its hardware implementation and the tests performed for the intended application. The process node alone cannot establish suitability for a particular security requirement.<\/p>\n

3. Can the 10 \u00d7 10 mm dimensions be used to estimate chips per wafer?<\/strong><\/h3>\n

The published dimensions refer to the package<\/strong>. Estimating dies per wafer requires the silicon die dimensions, wafer diameter and layout constraints. Estimating the number of usable chips also requires yield data or test results.<\/p>\n

Conclusion<\/strong><\/h2>\n

VGC v1.0 demonstrates a specific capability: a Vietnamese team translated a domestic cipher into an integrated circuit, measured its performance on silicon and brought it into a secure storage device. Its longer-term industrial significance will depend on how successfully that verified design can be adapted to future products, including signature devices and systems that protect data in transit.<\/p>\n

For manufacturers evaluating fabrication or metrology equipment, a useful starting point is the wafer material, the structure being processed and the acceptance criteria for the next step. These details allow an engineering team to select a suitable process, define the measurement and plan a trial under representative conditions. Contact PMAC to discuss your semiconductor process requirements<\/a>.<\/p>\n

PMAC Joint Stock Company<\/span><\/h3>\n

Ho Chi Minh City Office:<\/strong>
4th Floor, HUTECH Building, D1 Road, Saigon Hi-Tech Park, Tang Nhon Phu Ward, Ho Chi Minh City, Vietnam<\/p>\n

Hanoi Office:<\/strong>
22B O2, Linh Dam Peninsula, Hoang Liet Ward, Hanoi, Vietnam<\/p>\n

Hotline:<\/strong>\u00a0+84 387 235 878<\/p>\n

Facebook:<\/strong>\u00a0PMAC<\/a><\/p>\n

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\"PMAC

Author:<\/strong> PMAC \u2013 Nguyen Quoc Dung \u2013 Lab & Maintenance Center Chief<\/p><\/div>\n<\/div>\n<\/div>\n<\/div>\n","protected":false},"excerpt":{"rendered":"

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